(1) Field of the Invention
The present invention relates to an arithmetic processing apparatus, in particular to an arithmetic processing apparatus that has an encoder which is applicable to both of a Moving Picture Experts Group (MPEG) which is a coding standard of moving picture data and a Joint Photographic Experts Group (JPEG) which is a coding standard of still picture data, the encoder having a Motion Estimation (hereafter referred to as ME) circuit, a Discrete Cosine Transform (hereafter referred to as DCT) circuit, a digital filter and the like.
(2) Description of the Related Art
For instance, an encoder which applies to both MPEG and JPEG standards (hereafter referred to as MPEG/JPEG encoder) is build in a conventional digital still camera (hereafter referred to as DSC) having a function of shooting moving pictures.
The conventional MPEG/JPEG encoder needs, in MPEG processing, a high-performance ME circuit in order to detects a direction and size of a motion vector inside a frame and inter-frames of the moving picture data. Thus, an ME operation becomes dominant compared to a DCT operation in MPEG processing. In JPEG processing for a mega pixel class, it needs a DCT circuit having a higher processing capability than that of the DCT circuit used in the MPEG processing so that a DCT operation becomes dominant. Furthermore, it needs a digital filter as a common circuit for MPEG processing and JPEG processing.
FIG. 1 is a block diagram showing an example of a configuration of a DSC having the MPEG/JPEG encoder. In FIG. 1, 1901 shows an optical unit constituted of optical components such as lens. An optical signal from a subject to be imaged is, via the optical unit 1901, inputted to an image sensor 1902 such as CCD and converted into an electric signal. 1903 shows an analog signal processing/timing signal generating unit. The timing signal generating unit (TG) generates a timing signal which drives the image sensor 1902. The analog signal processing unit 1903 performs, on the analog signal from the image sensor 1902, processing such as correlated double sampling (CDS), automatic gain control (AGC) and A/D conversion, and converts it to a digital image data. The picture data calculated as described above is stored into a memory 1905 via a memory controller 1904.
The picture data stored in the memory 1905 is inputted to a MPEG/JPEG encoder 1906 via the memory controller 1904. The MPEG/JPEG encoder 1906 encodes, when the picture data stored in the memory 1905 is moving picture data, the inputted picture data by the MPEG processing circuit. The MPEG processing circuit performs coding by a motion compensation inter-frame prediction coding using a temporal correlation, the DCT using a Distributed Arithmetic (hereafter referred to as DA) method as an orthogonal coding using a spatial correlation, a quantization which weights coefficients not to assign a code to coefficients in high-frequency which has lesser visual effects in order to suppress an amount of coding generation, and a Huffman coding as an entropy coding (variable length coding) for assigning a shorter code stream to a coefficient with high generation probability using a bias of the generation probability (generation ratio).
On the other hand, when the picture data stored in the memory 1905 is still picture data, the MPEG/JPEG encoder 1906 encodes the inputted still picture data using the JPEG processing circuit which performs coding by the DCT using the DA method, quantization and Huffman coding.
The coded data sent from the MPEG/JPEG encoder 1906 is stored into the memory 1905, or is written into a memory card 1908 via a memory card interface (I/F) 1907. Note that a CPU 1909 which controls the analog signal processing/timing signal generating unit 1903, the MPEG/JPEG encoder 1906 and the memory card I/F 1907.
As described above, in the MPEG processing circuit inside the MPEG/JPEG encoder 1906, the ME circuit is included for performing motion compensated interframe prediction coding. The ME circuit searches, for instance per macroblock of 16×16 pixels, whether or not a similar picture data exists in a coded frame.
It is assumed that the ME circuit, for instance when it searches all of one frame whose picture size is 640×480 pixels (40×30 macroblock), performs Sum of Absolute Differences (hereafter referred to as SAD) operations of 16×16 pixels while shifting 640 pixels in a horizontal direction and 480 lines in a vertical direction. In this case, one SAD operation needs, for one macroblock, 256 times of the subtract operation and 256 times of add operation for calculating a sum. That is, the total of 512 times of add-subtract processing is needed. Thus, 512×640×480×40×30=188743680000 times, about 1887 billion times of add-subtract processing are performed for one frame.
Furthermore, when two thirds of 30 frames per second of the picture data to be processed are two bi-predictive coded B pictures, the ME circuit needs vast number of arithmetic processing as many as 188 billion×30×5/3=94371 billion times per second. This becomes a factor of determining an amount of arithmetic processing (circuit scale, power consumption) in the MPEG processing circuit.
Also, as described above, the DCT circuit for performing spatial redundant compression is included in the JPEG processing circuit inside the MPEG/JPEG encoder 1906. The DCT circuit splits two-dimensional pixel data (YUV data) into blocks each having 8×8 pixels and performs one-dimensional DCT in horizontal and vertical directions.
The number of blocks for which the DCT circuit has to perform, on pixel data in 3 million pixel class sent from the CCD as an image sensor, arithmetic processing by a continuous exposure mode for 4 frame per second is 3 million×4/(8×8)≈0.187500 per second. Further, in order to calculate a preset coding amount, when quantization matrix is adjusted and the arithmetic processing is redone after the side DCT, the number of blocks for which the arithmetic processing is performed is 187500×2=375000.
The DCT circuit is also included in the MPEG processing circuit. However, even if the picture size is 64×480 pixels and 30 frames per second, the number of blocks for which the DCT circuit performs the arithmetic processing is 640×480×30/(8×8)≈144000 per second.
Accordingly, the DCT circuit included in the JPEG processing circuit needs an amount of the arithmetic processing which is 2.5 times or more of that of the DCT circuit in the MPEG processing circuit. This becomes a factor of determining the amount of the arithmetic processing (circuit scale, power consumption) in the JPEG processing circuit.
The conventional technology is, for instance, disclosed in Japanese-Laid Open Patent Application No. 2001-84242, Japanese-Laid Open Patent Application No. H7-264583, Japanese-Laid Open Patent Application No. H10-83388 and the like.
As described above, the conventional MPEG/JPEG encoder needs a high-performance ME circuit for the MPEG processing and needs a high-processing performance DCT circuit for the JPEG processing but it cannot mutually use both circuits for the MPEG processing and the JPEG processing. Thus, the conventional MPEG/JPEG encoder has a problem that each circuit is separately set so that a circuit scale is enlarged and the power consumption is increased.